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PENTIUM(R) PROCESSOR at iCOMP(R) INDEX 610\75 MHz
Compatible with Large Software Base - MS-DOS*, Windows*, OS/2*, UNIX* 32-Bit CPU with 64-Bit Data Bus Superscalar Architecture - Two Pipelined Integer Units Are Capable of 2 Instructions/Clock - Pipelined Floating Point Unit Separate Code and Data Caches - 8K Code, 8K Writeback Data - MESI Cache Protocol Advanced Design Features - Branch Prediction - Virtual Mode Extensions
n n n n n n
3.3V BiCMOS Silicon Technology 4M Pages for Increased TLB Hit Rate IEEE 1149.1 Boundary Scan Internal Error Detection Features SL Enhanced Power Management Features - System Management Mode - Clock Control Fractional Bus Operation - 75-MHz Core / 50-MHz Bus
The Pentium(R) processor is fully compatible with the entire installed base of applications for DOS*, Windows*, OS/2*, and UNIX*, and all other software that runs on any earlier Intel 8086 family product. The Pentium processor's superscalar architecture can execute two instructions per clock cycle. Branch prediction and separate caches also increase performance. The pipelined floating-point unit delivers workstation level performance. Separate code and data caches reduce cache conflicts while remaining software transparent. The Pentium processor (610\75) has 3.3 million transistors, is built on Intel's advanced 3.3V BiCMOS silicon technology, and has full SL Enhanced power management features, including System Management Mode (SMM) and clock control. The additional SL Enhanced features, 3.3V operation, and the TCP package, which are not available in the Pentium processor (510\60, 567\66), make the Pentium processor (610\75) TCP ideal for enabling mobile Pentium processor designs. The Pentium processor may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available upon request.
June 1997
Order Number 242323-004
PENTIUM PROCESSOR (610\75)
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CONTENTS
PAGE
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PAGE
1.0. INTRODUCTION................................................2 1.1. Pentium(R) Processor (610\75) SPGA Specifications and Differences from the TCP Package.............................................................2 2.0. MICROPROCESSOR ARCHITECTURE OVERVIEW ...........................................................3 2.1. Pentium(R) Processor Family Architecture........4 3.0. TCP PINOUT......................................................7 3.1. TCP Pinout and Pin Descriptions...................7 3.1.1. Pentium(R) Processor (610\75) TCP PINOUT .........................................................7 3.1.2. PIN CROSS REFERENCE TABLE FOR Pentium(R) Processor (610\75) TCP................8 3.2. Design Notes................................................10 3.3. Quick Pin Reference.....................................10 3.4. Pin Reference Tables...................................19 3.5. Pin Grouping According to Function.............22 4.0. Pentium(R) Processor (610\75) TCP ELECTRICAL SPECIFICATIONS......................23 4.1. Maximum Ratings.........................................23 4.2. DC Specifications.........................................23
4.3. AC Specifications..........................................25 4.3.1. POWER AND GROUND.......................25 4.3.2. DECOUPLING RECOMMENDATIONS25 4.3.3. CONNECTION SPECIFICATIONS ......26 4.3.4. AC TIMINGS FOR A 50-MHZ BUS.......26 4.4. I/O Buffer Models..........................................35 4.4.1. BUFFER MODEL PARAMETERS........38 4.4.2. SIGNAL QUALITY SPECIFICATIONS .39 4.4.2.1. Ringback.........................................40 4.4.2.2. Settling Time...................................40 5.0. Pentium(R) Processor (610\75) TCP MECHANICAL SPECIFICATIONS.....................42 5.1. TCP Package Mechanical Diagrams............42 6.0. Pentium(R) Processor (610\75) TCP THERMAL SPECIFICATIONS...............................................47 6.1. Measuring Thermal Values...........................47 6.2. Thermal Equations........................................47 6.3. TCP Thermal Characteristics ........................47 6.4. PC Board Enhancements ..............................47 6.4.1. STANDARD TEST BOARD CONFIGURATION ......................................48
Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The Pentium(R) processor may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be obtained from: Intel Corporation P.O. Box 7641 Mt. Prospect IL 60056-7641 or call 1-800-879-4683 or visit Intel's website at http:\\www.intel.com Copyright (c) Intel Corporation 1996, 1997. * Third-party brands and names are the property of their respective owners.
PENTIUM PROCESSOR (610\75)
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1.0. INTRODUCTION
Intel is now manufacturing its latest version of the Pentium(R) processor family that is designed specifically for mobile systems, with a core frequency of 75 MHz and a bus frequency of 50 MHz. The Pentium processor (610\75) is provided in the TCP (Tape Carrier Package) and SPGA packages, and has all of the advanced features of the Pentium processor (735\90, 815\100) . The new Pentium processor (610\75) TCP package has several features which allow highperformance notebooks to be designed with the Pentium processor, including the following: * TCP package dimensions are ideal for small form-factor designs. * The TCP package has resistance characteristics. superior thermal
List of related documents: * Pentium(R) Processor Family Developer' s Manual, Vol. 1 (Order Number: 241428) * Pentium(R) Processor Family Developer' s Manual, Vol. 3: Architecture and Programming Manual (Order Number: 241430)
1.1. Pentium Processor (610\75) SPGA Specifications and Differences from the TCP Package
This section provides references to the Pentium processor (610\75) SPGA specifications and describes the major differences between the Pentium processor (610\75) SPGA and TCP packages. All Pentium processor (610\75) SPGA specifications, with the exception of power consumption, are identical to the Pentium processor (735\90, 815\100) specifications provided in the Pentium(R) Processor Family Developer' Manual, Volume 1. See Tables 8 and s 11 in section 4.2 for the Pentium processor (610\75) SPGA and TCP power specifications. The following features have been eliminated for the Pentium processor (610\75) TCP: the Upgrade feature, the Dual Processing (DP) feature, and the Master/Checker functional redundancy feature. Table 1 lists the corresponding pins which exist on the Pentium processor (610\75) SPGA but have been removed on the Pentium processor (610\75) TCP.
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* 3.3V VCC reduces power consumption by half (in both the TCP and SPGA packages). * The SL Enhanced feature set, which was initially implemented in the Intel486TM CPU. The architecture and internal features of the Pentium processor (610\75) TCP and SPGA packages are identical to those of the Pentium processor (735\90, 815\100), although several features have been eliminated for the Pentium processor (610\75) TCP, as described in section 1.1. This document should be used in conjunction with the Pentium processor documents listed below.
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PENTIUM PROCESSOR (610\75)
Table 1. SPGA Signals Removed in TCP Signal ADSC# Function Additional Address Status. This signal is mainly used for large or standalone L2 cache memory subsystem support required for high-performance desktop or server models. Additional Burst Ready. This signal is mainly used for large or standalone L2 cache memory subsystem support required for high-performance desktop or server models. CPU Type. This signal is used for dual processing systems. Dual/Primary processor identification. This signal is only used for an Upgrade processor. Functional Redundancy Checking. This signal is only used for error detection via processor redundancy, and requires two Pentium processors (master/checker). Private Bus Grant. This signal is only used for dual processing systems. Private Bus Request. This signal is used only for dual processing systems. Private Hit. This signal is only used for dual processing systems. Private Modified Hit. This signal is only used for dual processing systems. processor (610\75)" will be used in this document to refer to the Pentium processor at iCOMP rating 610\75 MHz. "Pentium Processor" will be used in this document to refer to the entire Pentium processor family in general. The Pentium processor family architecture contains all of the features of the Intel486 CPU family, and provides significant enhancements and additions including the following: * Superscalar Architecture * Dynamic Branch Prediction * Pipelined Floating-Point Unit * Improved Instruction Execution Time * Separate 8K Code and 8K Data Caches * Writeback MESI Protocol in the Data Cache * 64-Bit Data Bus * Bus Cycle Pipelining * Address Parity * Internal Parity Checking * Execution Tracing * Performance Monitoring * IEEE 1149.1 Boundary Scan * System Management Mode
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BRDYC#
CPUTYP D/P# FRCMC#
PBGNT# PBREQ# PHIT# PHITM#
The I/O buffer models provided in section 4.4 of this document apply to both the Pentium processor (610\75) TCP and SPGA packages, although the capacitance (Cp) and inductance (Lp) parameter values differ between the two packages. Also, the thermal parameters, TCASE max and CA, differ between the TCP and SPGA packages. For Pentium processor (610\75) SPGA values, refer to Chapters 24 and 26 of the Pentium(R) Processor Family Developer' Manual, Volume 1 . s
2.0. MICROPROCESSOR ARCHITECTURE OVERVIEW
The Pentium processor at iCOMP(R) rating 610\75 MHz extends the Intel Pentium family of microprocessors. It is compatible with the 8086/88, 80286, Intel386TM DX CPU, Intel386 SX CPU, Intel486TM DX CPU, Intel486 SX CPU, Intel486 DX2 CPUs, the Pentium processor at iCOMP Index 510\60 MHz and iCOMP Index 567\66 MHz, and the Pentium processor at iCOMP Index 735\90 MHz and iCOMP Index 815\100 MHz. The Pentium processor family consists of the new Pentium processor at iCOMP rating 610\75 MHz, described in this document, the original Pentium processor (510\60, 567\66), and the Pentium processor (735\90, 815\100). The name "Pentium 2
PENTIUM PROCESSOR (610\75)
* Virtual Mode Extensions writeback or writethrough on a line-by-line basis and follows the MESI protocol. The data cache tags are triple ported to support two data transfers and an inquire cycle in the same clock. The code cache is an inherently write-protected cache. The code cache tags are also triple ported to support snooping and split line accesses. Individual pages can be configured as cacheable or non-cacheable by software or hardware. The caches can be enabled or disabled by software or hardware. The Pentium processors have increased the data bus to 64 bits to improve the data transfer rate. Burst read and burst writeback cycles are supported by the Pentium processors. In addition, bus cycle pipelining has been added to allow two bus cycles to be in progress simultaneously. The Pentium processors' Memory Management Unit contains optional extensions to the architecture which allow 2-Mbyte and 4-Mbyte page sizes. The Pentium processors have added significant data integrity and error detection capability. Data parity checking is still supported on a byte-by-byte basis. Address parity checking, and internal parity checking features have been added along with a new exception, the ma chine check exception. As more and more functions are integrated on chip, the complexity of board level testing is increased. To address this, the Pentium processors have increased test and debug capability. The Pentium processors implement IEEE Boundary Scan (Standard 1149.1). In addition, the Pentium processors have specified 4 breakpoint pins that correspond to each of the debug registers and externally indicate a breakpoint match. Execution tracing provides external indications when an instruction has completed execution in either of the two internal pipelines, or when a branch has been taken. System Management Mode (SMM) has been implemented along with some extensions to the SMM architecture. Enhancements to the virtual 8086 mode have been made to increase performance by reducing the number of times it is necessary to trap to a vir tual 8086 monitor.
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2.1. Pentium (R) Processor Family Architecture
The application instruction set of the Pentium processor family includes the complete Intel486 CPU family instruction set with extensions to accommodate some of the additional functionality of the Pentium processors. All application software written for the Intel386 and Intel486 family microprocessors will run on the Pentium processors without modification. The on-chip memory management unit (MMU) is completely compatible with the Intel386 family and Intel486 family of CPUs. The Pentium processors implement several enhancements to increase performance. The two instruction pipelines and floating-point unit on Pentium processors are capable of independent operation. Each pipeline issues frequently used instructions in a single clock. Together, the dual pipes can issue two integer instructions in one clock, or one floating point instruction (under certain circumstances, two floating-point instructions) in one clock. Branch prediction is implemented in the Pentium processors. To support this, Pentium processors implement two prefetch buffers, one to prefetch code in a linear fashion, and one that prefetches code according to the BTB so the needed code is almost always prefetched before it is needed for execution. The floating-point unit has been completely redesigned over the Intel486 CPU. Faster algorithms provide up to 10X speed-up for common operations including add, multiply, and load. Pentium processors include separate code and data caches integrated on-chip to meet performance goals. Each cache is 8 Kbytes in size, with a 32-byte line size and is 2-way set associative. Each cache has a dedicated Translation Lookaside Buffer (TLB) to translate linear addresses to physical addresses. The data cache is configurable to be
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PENTIUM PROCESSOR (610\75)
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Figure 1. Pentium (R) Processor Block Diagram
4
PENTIUM PROCESSOR (610\75)
The block diagram shows the two instruction pipelines, the "u" pipe and the "v" pipe. The u-pipe can execute all integer and floating point instructions. The v-pipe can execute simple integer instructions and the FXCH floating-point instructions. The separate caches are shown, the code cache and data cache. The data cache has two ports, one for each of the two pipes (the tags are triple ported to allow simultaneous inquire cycles). The data cache has a dedicated Translation Lookaside Buffer (TLB) to translate linear addresses to the physical addresses used by the data cache. The code cache, branch target buffer and prefetch buffers are responsible for getting raw instructions into the execution units of the Pentium processor. Instructions are fetched from the code cache or from the external bus. Branch addresses are remembered by the branch target buffer. The code cache TLB translates linear addresses to physical addresses used by the code cache. The decode unit decodes the prefetched instructions so the Pentium processor can execute the instruction. The control ROM contains the microcode which controls the sequence of operations that must be performed to implement the Pentium processor architecture. The control ROM unit has direct control over both pipelines. The Pentium processors contain a pipelined floating-point unit that provides a significant floating-point performance advantage over previous generations of processors. The architectural features introduced in this section are more fully described in the Pentium(R) Processor Family Developer' Manual . s
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5
PENTIUM PROCESSOR (610\75)
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3.0. TCP PINOUT 3.1. TCP Pinout and Pin Desc riptions
3.1.1. Pentium (R) Processor (610\75) TCP PINOUT
Figure 2. Pentium (R) Processor (610\75) TCP Pinout
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PENTIUM PROCESSOR (610\75)
3.1.2. PIN CROSS REFERENCE TABLE FOR Pentium (R) Processor (610\75) TCP Table 2. TCP Pin Cross Reference by Pin Name Address A3 A4 A5 A6 A7 A8 219 222 223 227 228 231 A9 A10 A11 A12 A13 A14 234 237 238 242 245 248 A15 A16 A17 A18 A19 A20 251 254 255 259 262 265 Data D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 152 151 150 149 146 145 144 143 139 138 137 134 133 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 132 131 128 126 125 122 121 120 119 116 115 113 108 D26 D27 D28 D29 D30 D31 D32 D33 D34 D35 D36 D37 D38 107 106 105 102 101 100 96 95 94 93 90 89 88 D39 D40 D41 D42 D43 D44 D45 D46 D47 D48 D49 D50 D51 87 83 82 81 78 77 76 75 72 70 69 64 63 D52 D53 D54 D55 D56 D57 D58 D59 D60 D61 D62 D63 62 61 56 55 53 48 47 46 45 40 39 38 A21 A22 A23 A24 A25 A26 200 201 202 205 206 207 A27 A28 A29 A30 A31 208 211 212 213 214
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PENTIUM PROCESSOR (610\75)
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Table 2. TCP Pin Cross Reference by Pin Name (Contd.) Control A20M# ADS# AHOLD AP APCHK# BE0# BE1# BE2# BE3# BE4# BE5# BE6# BE7# BOFF# BP2 BP3 BRDY# 286 296 14 308 315 285 284 283 282 279 278 277 276 9 28 25 10 BREQ BUSCHK# CACHE# D/C# DP0 DP1 DP2 DP3 DP4 DP5 DP6 DP7 EADS# EWBE# FERR# FLUSH# HIT# APIC PICCLK PICD0 [DPEN#] 155 156 PICD1 [APICEN] 158 BF CLK 186 272 312 288 21 298 140 127 114 99 84 71 54 37 297 16 31 287 292 HITM# HLDA HOLD IERR# IGNNE# INIT INTR/LINT0 INV KEN# LOCK# M/IO# NA# NMI/LINT1 PCD PCHK# PEN# PM0/BP0 293 311 4 34 193 192 197 15 13 303 22 8 199 300 316 191 30 Clock Control STPCLK# 181 PM1/BP1 PRDY PWT R/S# RESET SCYC SMI# SMIACT# TCK TDI TDO TMS TRST# W/R# WB/WT# 29 318 299 198 270 273 196 319 161 163 162 164 167 289 5
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PENTIUM PROCESSOR (610\75)
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Table 2. TCP Pin Cross Reference by Pin Name (Contd.) Vcc 1* 2 6* 11* 17* 19 23 27* 33* 35 41* 43 49* 51 57* 59 65* 67 73 79 85 91 97 103 109 111* 117 123 129 135 141 147 153* 157* 160 165* 168* 170* 172* 174* 177* 178 180* 183* 188* Vss 3 7 12 18 20 24 26 32 36 42 44 50 52 58 60 66 68 74 80 86 92 98 104 110 112 118 124 130 136 142 148 154 159 166 169 171 173 176 179 182 187 189 194 203 NC 175 184 185 271 209 215 218 220 224 229 233 235 239 244 246 250 252 256 261 263 267 269 274 280 290 294 302 305 307 310 314 320 190* 195* 204 210 216 217* 221 225* 226 230 232* 236 240* 241 243* 247 249* 253 257* 258 260* 264 266* 268* 275 281 291 295 301 304* 306 309* 313 317*
NOTE: *These Vcc pins are 3.3V supplies for the Pentium processor (610\75) TCP but will be lower voltage pins on future offerings of this microprocessor family. All other V cc pins will remain at 3.3V.
3.2. Design Notes
For reliable operation, always connect unused inputs to an appropriate signal level. Unused active low inputs should be connected to Vcc. Unused active HIGH inputs should be connected to GND (Vss).
No Connect (NC) pins must remain unconnected. Connection of NC pins may result in component failure or incompatibility with processor steppings.
3.3. Quick Pin Reference
This section gives a brief functional description of each of the pins. For a detailed description, see the "Hardware Interface" chapter in the Pentium(R) Processor Family Developer' Manual , Volume 1. s 9
PENTIUM PROCESSOR (610\75)
Note that all input pins must meet their AC/DC specifications to guarantee proper functional behavior. The # symbol at the end of a signal name indicates that the active, or asserted state occurs when the signal is at a low voltage. When a # symbol is not present after the signal name, the signal is active, or asserted at the high voltage level.
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Table 3. Quick Pin Reference Symbol A20M# Type I Name and Function When the address bit 20 mask pin is asserted, the Pentium processor (610\75) emulates the address wraparound at 1 Mbyte which occurs on the 8086. When A20M# is asserted, the Pentium processor (610\75) masks physical address bit 20 (A20) before performing a lookup to the internal caches or driving a memory cycle on the bus. The effect of A20M# is undefined in protected mode. A20M# must be asserted only when the processor is in real mode. As outputs, the address lines of the processor along with the byte enables define the physical area of memory or I/O accessed. The external system drives the inquire address to the processor on A31-A5. The address status indicates that a new valid bus cycle is currently being driven by the Pentium processor (610\75) . In response to the assertion of address hold , the Pentium processor (610\75) will stop driving the address lines (A31-A3), and AP in the next clock. The rest of the bus will remain active so data can be returned or driven for previously issued bus cycles. Address parity is driven by the Pentium processor (610\75) with even parity information on all Pentium processor (610\75) generated cycles in the same clock that the address is driven. Even parity must be driven back to the Pentium processor (610\75) during inquire cycles on this pin in the same clock as EADS# to ensure that correct parity check status is indicated by the Pentium processor (610\75). The address parity check status pin is asserted two clocks after EADS# is sampled active if the Pentium processor (610\75) has detected a parity error on the address bus during inquire cycles. APCHK# will remain active for one clock each time a parity error is detected. The Advanced Programmable Interrupt Controller Enable pin enables or disables the on-chip APIC interrupt controller. If sampled high at the falling edge of RESET, the APIC is enabled. APICEN shares a pin with the Programmable Interrupt Controller Data 1 signal. The byte enable pins are used to determine which bytes must be written to external memory, or which bytes were requested by the CPU for the current cycle. The byte enables are driven in the same clock as the address lines (A31-3). The lower four byte enables (BE3#-BE0#) are used on the Pentium processor (610\75) as APIC ID inputs and are sampled at RESET.
A31-A3
I/O
ADS# AHOLD
O I
AP
I/O
APCHK#
O
[APICEN] PICD1
I
BE7#-BE5# BE4#-BE0#
O I/O
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PENTIUM PROCESSOR (610\75)
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Table 3. Quick Pin Reference (Contd.) Symbol [BF] Type I Name and Function Bus Frequency determines the bus -to-core frequency ratio. BF is sampled at RESET, and cannot be changed until another non-warm ( 1 ms) assertion of RESET. Additionally, BF must not change values while RESET is active. For proper operation of the Pentium processor (610\75) this pin should be strapped high or low. When BF is strapped to V cc, the processor will operate at a 2/3 bus/core frequency ratio. When BF is strapped to V ss, the processor will operate at a 1/2 bus/core frequency ratio. If BF is left floating, the Pentium processor (610\75) defaults to a 2/3 bus ratio. Note the Pentium processor (610\75) will not operate at a 1/2 bus/core frequency ratio. The backoff input is used to abort all outstanding bus cycles that have not yet completed. In response to BOFF#, the Pentium processor (610\75) will float all pins normally floated during bus hold in the next clock. The processor remains in bus hold until BOFF# is negated, at which time the Pentium processor (610\75) restarts the aborted bus cycle(s) in their entirety. The breakpoint pins (BP3-0) correspond to the debug registers, DR3-DR0. These pins externally indicate a breakpoint match when the debug registers are programmed to test for breakpoint matches. BP1 and BP0 are multiplexed with the performance monitoring pins (PM1 and PM0). The PB1 and PB0 bits in the Debug Mode Control Register determine if the pins are configured as breakpoint or performance monitoring pins. The pins come out of RESET configured for performance monitoring. BRDY# I The burst ready input indicates that the external system has presented valid data on the data pins in response to a read or that the external system has accepted the Pentium processor (610\75) data in response to a write request. This signal is sampled in the T2, T12 and T2P bus states. The bus request output indicates to the external system that the Pentium processor (610\75) has internally generated a bus request. This signal is always driven whether or not the Pentium processor (610\75) is driving its bus. The bus check input allows the system to signal an unsuccessful completion of a bus cycle. If this pin is sampled active, the Pentium processor (610\75) will latch the address and control signals in the machine check registers. If, in addition, the MCE bit in CR4 is set, the Pentium processor (610\75) will vector to the machine check exception. For Pentium processor (610\75) -initiated cycles the cache pin indicates internal cacheability of the cycle (if a read), and indicates a burst writeback cycle (if a write). If this pin is driven inactive during a read cycle, the Pentium processor (610\75) will not cache the returned data, regardless of the state of the KEN# pin. This pin is also used to determine the cycle length (number of transfers in the cycle).
BOFF#
I
BP[3:2] PM/BP[1:0]
O
BREQ
O
BUSCHK#
I
CACHE#
O
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PENTIUM PROCESSOR (610\75)
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Table 3. Quick Pin Reference (Contd.) Symbol CLK Type I Name and Function The clock input provides the fundamental timing for the Pentium processor (610\75). Its frequency is the operating frequency of the Pentium processor (610\75) external bus and requires TTL levels. All external timing parameters except TDI, TDO, TMS, TRST#, and PICD0-1 are specified with respect to the rising edge of CLK. The data/code output is one of the primary bus cycle definition pins. It is driven valid in the same clock as the ADS# signal is asserted. D/C# distinguishes between data and code or special cycles. These are the 64 data lines for the processor. Lines D7-D0 define the least significant byte of the data bus; lines D63-D56 define the most significant byte of the data bus. When the CPU is driving the data lines, they are driven during the T2, T12, or T2P clocks for that cycle. During reads, the CPU samples the data bus when BRDY# is returned. These are the data parity pins for the processor. There is one for each byte of the data bus. They are driven by the Pentium processor (610\75) with even parity information on writes in the same clock as write data. Even parity information must be driven back to the Pentium processor (610\75) on these pins in the same clock as the data to ensure that the correct parity check status is indicated by the Pentium processor (610\75) . DP7 applies to D63-D56; DP0 applies to D7-D0. Dual processing enable is an output of the Dual processor and an input of the Primary processor. The Dual processor drives DPEN# low to the Primary processor at RESET to indicate that the Primary processor should enable dual processor mode. Since the dual processing feature is not supported on the Pentium processor (610\75) TCP package, DPEN# should never be asserted (low) at RESET. DPEN# shares a pin with PICD0. This signal indicates that a valid external address has been driven onto the Pentium processor (610\75) address pins to be used for an inquire cycle. The external write buffer empty input, when inactive (high), indicates that a write cycle is pending in the external system. When the Pentium processor (610\75) generates a write, and EWBE# is sampled inactive, the Pentium processor (610\75) will hold off all subsequent writes to all E- or M-state lines in the data cache until all write cycles have completed, as indicated by EWBE# being active. The floating point error pin is driven active when an unmasked floating point error occurs. FERR# is similar to the ERROR# pin on the Intel387TM math coprocessor. FERR# is included for compatibility with systems using DOS-type floating point error reporting.
D/C#
O
D63-D0
I/O
DP7-DP0
I/O
[DPEN#] PICD0
I/O
EADS# EWBE#
I I
FERR#
O
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PENTIUM PROCESSOR (610\75)
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Table 3. Quick Pin Reference (Contd.) Symbol FLUSH# Type I Name and Function When asserted, the cache flush input forces the Pentium processor (610\75) to write back all modified lines in the data cache and invalidate its internal caches. A Flush Acknowledge special cycle will be generated by the Pentium processor (610\75) indicating completion of the writeback and invalidation. If FLUSH# is sampled low when RESET transitions from high to low, tristate test mode is entered. HIT# O The hit indication is driven to reflect the outcome of an inquire cycle. If an inquire cycle hits a valid line in either the Pentium processor (610\75) data or instruction cache, this pin is asserted two clocks after EADS# is sampled asserted. If the inquire cycle misses the Pentium processor (610\75) cache, this pin is negated two clocks after EADS#. This pin changes its value only as a result of an inquire cycle and retains its value between the cycles. The hit to a modified line output is driven to reflect the outcome of an inquire cycle. It is asserted after inquire cycles which resulted in a hit to a modified line in the data cache. It is used to inhibit another bus master from accessing the data until the line is completely written back. The bus hold acknowledge pin goes active in response to a hold request driven to the processor on the HOLD pin. It indicates that the Pentium processor (610\75) has floated most of the output pins and relinquished the bus to another local bus master. When leaving bus hold, HLDA will be driven inactive and the Pentium processor (610\75) will resume driving the bus. If the Pentium processor (610\75) has a bus cycle pending, it will be driven in the same clock that HLDA is de-asserted. In response to the bus hold request , the Pentium processor (610\75) will float most of its output and input/output pins and assert HLDA after completing all outstanding bus cycles. The Pentium processor (610\75) will maintain its bus in this state until HOLD is de-asserted. HOLD is not recognized during LOCK cycles. The Pentium processor (610\75) will recognize HOLD during reset. The internal error pin is used to indicate internal parity errors. If a parity error occurs on a read from an internal array, the Pentium processor (610\75) will assert the IERR# pin for one clock and then shutdown. This is the ignore numeric error input. This pin has no effect when the NE bit in CR0 is set to 1. When the CR0.NE bit is 0, and the IGNNE# pin is asserted, the Pentium processor (610\75) will ignore any pending unmasked numeric exception and continue executing floating-point instructions for the entire duration that this pin is asserted. When the CR0.NE bit is 0, IGNNE# is not asserted, a pending unmasked numeric exception exists (SW.ES = 1), and the floating-point instruction is one of FINIT, FCLEX, FSTENV, FSAVE, FSTSW, FSTCW, FENI, FDISI, or FSETPM, the Pentium processor (610\75) will execute the instruction in spite of the pending exception. When the CR0.NE bit is 0, IGNNE# is not asserted, a pending unmasked numeric exception exists (SW.ES = 1), and the floating-point instruction is one other than FINIT, FCLEX, FSTENV, FSAVE, FSTSW, FSTCW, FENI, FDISI, or FSETPM, the Pentium processor (610\75) will stop execution and wait for an external interrupt.
HITM#
O
HLDA
O
HOLD
I
IERR#
O
IGNNE#
I
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PENTIUM PROCESSOR (610\75)
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Table 3. Quick Pin Reference (Contd.) Symbol INIT Type I Name and Function The Pentium processor (610\75) initialization input pin forces the Pentium processor (610\75) to begin execution in a known state. The processor state after INIT is the same as the state after RESET except that the internal caches, write buffers, and floating point registers retain the values they had prior to INIT. INIT may NOT be used in lieu of RESET after power up. If INIT is sampled high when RESET transitions from high to low, the Pentium processor (610\75) will perform built-in self test prior to the start of program execution. INTR / LINT0 I An active maskable interrupt input indicates that an external interrupt has been generated. If the IF bit in the EFLAGS register is set, the Pentium processor (610\75) will generate two locked interrupt acknowledge bus cycles and vector to an interrupt handler after the current instruction execution is completed. INTR must remain active until the first interrupt acknowledge cycle is generated to assure that the interrupt is recognized. If the local APIC is enabled, this pin becomes local interrupt 0 . INV I The invalidation input determines the final cache line state (S or I) in case of an inquire cycle hit. It is sampled together with the address for the inquire cycle in the clock EADS# is sampled active. The cache enable pin is used to determine whether the current cycle is cacheable or not and is consequently used to determine cycle length. When the Pentium processor (610\75) generates a cycle that can be cached (CACHE# asserted) and KEN# is active, the cycle will be transformed into a burst line fill cycle. If the APIC is enabled, this pin is local interrupt 0 . If the APIC is disabled, this pin is interrupt. If the APIC is enabled, this pin is local interrupt 1 . If the APIC is disabled, this pin is non-maskable interrupt . The bus lock pin indicates that the current bus cycle is locked. The Pentium processor (610\75) will not allow a bus hold when LOCK# is asserted (but AHOLD and BOFF# are allowed). LOCK# goes active in the first clock of the first locked bus cycle and goes inactive after the BRDY# is returned for the last locked bus cycle. LOCK# is guaranteed to be de-asserted for at least one clock between back-to-back locked cycles. The memory/input-output is one of the primary bus cycle definition pins. It is driven valid in the same clock as the ADS# signal is asserted. M/IO# distinguishes between memory and I/O cycles.
KEN#
I
LINT0/INTR LINT1/NMI LOCK#
I I O
M/IO#
O
14
PENTIUM PROCESSOR (610\75)
(R)
Table 3. Quick Pin Reference (Contd.) Symbol NA# Type I Name and Function An active next address input indicates that the external memory system is ready to accept a new bus cycle although all data transfers for the current cycle have not yet completed. The Pentium processor (610\75) will issue ADS# for a pending cycle two clocks after NA# is asserted. The Pentium processor (610\75) supports up to 2 outstanding bus cycles. The non-maskable interrupt request signal indicates that an external nonmaskable interrupt has been generated. If the local APIC is enabled, this pin becomes local interrupt 1 . PCD O The page cache disable pin reflects the state of the PCD bit in CR3, the Page Directory Entry, or the Page Table Entry. The purpose of PCD is to provide an external cacheability indication on a page-by-page basis. The parity check output indicates the result of a parity check on a data read. It is driven with parity status two clocks after BRDY# is returned. PCHK# remains low one clock for each clock in which a parity error was detected. Parity is checked only for the bytes on which valid data is returned. The parity enable input (along with CR4.MCE) determines whether a machine check exception will be taken as a result of a data parity error on a read cycle. If this pin is sampled active in the clock a data parity error is detected, the Pentium processor (610\75) will latch the address and control signals of the cycle with the parity error in the machine check registers. If, in addition, the machine check enable bit in CR4 is set to "1", the Pentium processor (610\75) will vector to the machine check exception before the beginning of the next instruction. The APIC interrupt controller serial data bus clock is driven into the programmable interrupt controller clock input of the Pentium processor (610\75). Programmable interrupt controller data lines 0-1 of the Pentium processor (610\75) comprise the data portion of the APIC 3-wire bus. They are opendrain outputs that require external pull-up resistors. These signals share pins with DPEN# and APICEN. These pins function as part of the performance monitoring feature. The breakpoint 1-0 pins are multiplexed with the performance monitoring 1 -0 pins. The PB1 and PB0 bits in the Debug Mode Control Register determine if the pins are configured as breakpoint or performance monitoring pins. The pins come out of RESET configured for performance monitoring. PRDY O The probe ready output pin indicates that the processor has stopped normal execution in response to the R/S# pin going active, or Probe Mode being entered. The page writethrough pin reflects the state of the PWT bit in CR3, the page directory entry, or the page table entry. The PWT pin is used to provide an external writeback indication on a page-by-page basis.
NMI/LINT1
I
PCHK#
O
PEN#
I
PICCLK
I
PICD0-1 [DPEN#] [APICEN] PM/BP[1:0]
I/O
O
PWT
O
15
PENTIUM PROCESSOR (610\75)
(R)
Table 3. Quick Pin Reference (Contd.) Symbol R/S# Type I Name and Function The run / stop input is an asynchronous, edge-sensitive interrupt used to stop the normal execution of the processor and place it into an idle state. A high to low transition on the R/S# pin will interrupt the processor and cause it to stop execution at the next instruction boundary. RESET forces the Pentium processor (610\75) to begin execution at a known state. All the Pentium processor (610\75) internal caches will be invalidated upon the RESET. Modified lines in the data cache are not written back. FLUSH# and INIT are sampled when RESET transitions from high to low to determine if tristate test mode will be entered, or if BIST will be run. The split cycle output is asserted during misaligned LOCKed transfers to indicate that more than two cycles will be locked together. This signal is defined for locked cycles only. It is undefined for cycles which are not locked. The system management interrupt causes a system management interrupt request to be latched internally. When the latched SMI# is recognized on an instruction boundary, the processor enters System Management Mode. An active system management interrupt active output indicates that the processor is operating in System Management Mode. Assertion of the stop clock input signifies a request to stop the internal clock of the Pentium processor (610\75) thereby causing the core to consume less power. When the CPU recognizes STPCLK#, the processor will stop execution on the next instruction boundary, unless superseded by a higher priority interrupt, and generate a Stop Grant Acknowledge cycle. When STPCLK# is asserted, the Pentium processor (610\75) will still res pond to external snoop requests. The testability clock input provides the clocking function for the Pentium processor (610\75) boundary scan in accordance with the IEEE Boundary Scan interface (Standard 1149.1). It is used to clock state information and data into and out of the Pentium processor (610\75) during boundary scan. The test data input is a serial input for the test logic. TAP instructions and data are shifted into the Pentium processor (610\75) on the TDI pin on the rising edge of TCK when the TAP controller is in an appropriate state. The test data output is a serial output of the test logic. TAP instructions and data are shifted out of the Pentium processor (610\75) on the TDO pin on TCK's falling edge when the TAP controller is in an appropriate state. The value of the test mode select input signal sampled at the rising edge of TCK controls the sequence of TAP controller state changes. When asserted, the test reset input allows the TAP controller to be asynchronously initialized.
RESET
I
SCYC
O
SMI#
I
SMIACT# STPCLK#
O I
TCK
I
TDI
I
TDO
O
TMS TRST#
I I
16
PENTIUM PROCESSOR (610\75)
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Table 3. Quick Pin Reference (Contd.) Symbol Vcc Vss W/R# Type I I O Name and Function The Pentium processor (610\75) has 79 3.3V power inputs. The Pentium processor (610\75) has 72 ground inputs. Write/read is one of the primary bus cycle definition pins. It is driven valid in the same clock as the ADS# signal is asserted. W/R# distinguishes between write and read cycles. The writeback/writethrough input allows a data cache line to be defined as writeback or writethrough on a line-by-line basis. As a result, it determines whether a cache line is initially in the S or E state in the data cache.
WB/WT#
I
3.4. Pin Reference Tables
Table 4. Output Pins Name ADS# APCHK# BE7#-BE5# BREQ CACHE# FERR# HIT# HITM# HLDA IERR# LOCK# M/IO#, D/C#, W/R# PCHK# BP3-2, PM1/BP1, PM0/BP0 PRDY PWT, PCD SCYC SMIACT# TDO Low Low Low High Low Low Low Low High Low Low n/a Low High High High High Low n/a All states except Shift-DR and Shift-IR Bus Hold, BOFF# Bus Hold, BOFF# Bus Hold, BOFF# Bus Hold, BOFF# Bus Hold, BOFF# Bus Hold, BOFF# Active Level When Floated Bus Hold, BOFF#
NOTE: All output and input/output pins are floated during tristate test mode (except TDO).
17
PENTIUM PROCESSOR (610\75)
Table 5. Input Pins Name A20M# AHOLD BF BOFF# BRDY# BUSCHK# CLK EADS# EWBE# FLUSH# HOLD IGNNE# INIT INTR INV KEN# NA# NMI PEN# PICCLK R/S# RESET SMI# STPCLK# TCK TDI TMS TRST# WB/WT# Active Level Low High High Low Low Low n/a Low Low Low High Low High High High Low Low High Low High n/a High Low Low n/a n/a n/a Low n/a Synchronous/TCK Synchronous/TCK Asynchronous Synchronous Synchronous Synchronous Asynchronous Synchronous Asynchronous Asynchronous Asynchronous Synchronous Synchronous Synchronous Asynchronous Synchronous Asynchronous Asynchronous Asynchronous Asynchronous Asynchronous Pullup Pullup Pullup Pullup Pullup Pullup First BRDY#/NA# TCK TCK Pullup Pullup BRDY# EADS# First BRDY#/NA# Bus State T2,TD,T2P BRDY# Synchronous/ Asynchronous Asynchronous Synchronous Synchronous/RESET Synchronous Synchronous Synchronous Pullup Bus State T2, T12, T2P BRDY# Pullup Internal resistor Qualified
(R)
18
PENTIUM PROCESSOR (610\75)
Table 6. Input/Output Pins Name A31-A3 AP BE4#-BE0# D63-D0 DP7-DP0 PICD0[DPEN#] PICD1[APICEN]
NOTES: All output and input/output pins are floated during tristate test mode (except TDO). *BE3#-BE0# have pulldowns during RESET only.
(R)
Active Level n/a n/a Low n/a n/a
When Floated Address Hold, Bus Hold, BOFF# Address Hold, Bus Hold, BOFF# Bus Hold, BOFF# Bus Hold, BOFF# Bus Hold, BOFF#
Qualified (when an input) EADS# EADS# RESET BRDY# BRDY#
Internal Resistor
Pulldown*
Pullup Pulldown
19
PENTIUM PROCESSOR (610\75)
(R)
3.5. Pin Grouping According to Function
Table 7 organizes the pins with respect to their function. Table 7. Pin Functional Grouping Function Clock Initialization Address Bus Address Mask Data Bus Address Parity APIC Support Data Parity Internal Parity Error System Error Bus Cycle Definition Bus Control Page Cacheability Cache Control Cache Snooping/Consistency Cache Flush Write Ordering Bus Arbitration Interrupts Floating Point Error Reporting System Management Mode TAP Port Breakpoint/Performance Monitoring Clock Control Probe Mode CLK RESET, INIT A31-A3, BE7# - BE0# A20M# D63-D0 AP, APCHK# PICCLK, PICD0-1 DP7-DP0, PCHK#, PEN# IERR# BUSCHK# M/IO#, D/C#, W/R#, CACHE#, SCYC, LOCK# ADS#, BRDY#, NA# PCD, PWT KEN#, WB/WT# AHOLD, EADS#, HIT#, HITM#, INV FLUSH# EWBE# BOFF#, BREQ, HOLD, HLDA INTR, NMI FERR#, IGNNE# SMI#, SMIACT# TCK, TMS, TDI, TDO, TRST# PM0/BP0, PM1/BP1, BP3-2 STPCLK# R/S#, PRDY Pins
20
PENTIUM PROCESSOR (610\75)
(R)
4.0. Pentium Processor (610\75) TCP ELECTRICAL SPECIFICATIONS 4.1. Maximum Ratings
The following values are stress ratings only. Functional operation at the maximum ratings is not implied or guaranteed. Functional operating conditions are given in the AC and DC specification tables. Extended exposure to the maximum ratings may affect device reliability. Furthermore, although the Pentium processor (610\75) contains protective circuitry to resist damage from static electric discharge, always take precautions to avoid high static voltages or electric fields. Case temperature under bias ......... -65 to 110 C C Storage temperature....................... -65 to 150 C C 3V Supply voltage with respect to V ss ........................... -0.5V to +4.6V 3V Only Buffer DC Input Voltage .... -0.5V to V cc + 0.5; not to exceed 4.6V 5V Safe Buffer DC Input Voltage .........................-0.5V to 6.5V
(2)
(R)
NOTES: 1. Applies to CLK and PICCLK. 2. Applies to all Pentium processor (610\75) inputs except CLK and PICCLK. 3. See Table 9.
WARNING Stressing the device beyond the "Absolute Maximum Ratings" may cause permanent damage. These are stress ratings only. Operation beyond the "Operating Conditions" is not recommended and extended exposure beyond the "Operating Conditions" may affect device reliability.
4.2. DC Specifications
Tables 8, 9, and 10 list the DC specifications which apply to the Pentium processor (610\75). The Pentium processor (610\75) is a 3.3V part internally. The CLK and PICCLK inputs may be a 3.3V or 5V inputs. Since the 3.3V (5V safe) input levels defined in Table 9 are the same as the 5V TTL levels, the CLK and PICCLK inputs are compatible with existing 5V clock drivers. The power dissipation specification in Table 11 is provided for design of thermal solutions during operation in a sustained maximum level. This is the worst-case power the device would dissipate in a system for a sustained period of time. This number is used for design of a thermal solution for the device.
(1,3)
Table 8. 3.3V DC Specifications TCASE = 0 to 95 V cc = 3.3V 5% C; Symbol VIL3 VIH3 VOL3 VOH3 ICC3 Parameter Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Power Supply Current 2.4 2650 Min -0.3 2.0 Max 0.8 Vcc+0.3 0.4 Unit V V V V mA Notes TTL Level (3) TTL Level (3) TTL Level (1) (3) TTL Level (2) (3) @75 MHz (4)
NOTES: 1. Parameter measured at 4 mA. 2. Parameter measured at 3 mA. 3. 3.3V TTL levels apply to all signals except CLK and PICCLK. 4. This value should be used for power supply design. It was determined using a worst-case instruction mix and V cc + 5%. Power supply transient response and decoupling capacitors must be sufficient to handle the instantaneous current changes occurring during transitions from stop clock to full active modes. For more information, refer to section 4.3.2.
21
PENTIUM PROCESSOR (610\75)
(R)
Table 9. 3.3V (5V Safe) DC Specifications Symbol VIL5 VIH5 Parameter Input Low Voltage Input High Voltage Min -0.3 2.0 Max 0.8 5.55 Unit V V Notes TTL Level (1) TTL Level (1)
NOTES: 1. Applies to CLK and PICCLK only.
Table 10. Input and Output Characteristics Symbol CIN CO CI/O CCLK CTIN CTOUT CTCK ILI ILO IIH IIL Parameter Input Capacitance Output Capacitance I/O Capacitance CLK Input Capacitance Test Input Capacitance Test Output Capacitance Test Clock Capacitance Input Leakage Current Output Leakage Current Input Leakage Current Input Leakage Current Min Max 15 20 25 15 15 20 15 15 15 200 -400 Unit pF pF pF pF pF pF pF A A A A (4) (4) (4) (4) (4) (4) (4) 0 < V IN < V CC3 (1) 0 < V IN < V CC3 (1) VIN = 2.4V (3) VIN = 0.4V (2) Notes
NOTES: 1. This parameter is for input without pull up or pull down. 2. This parameter is for input with pull up. 3. This parameter is for input with pull down. 4. Guaranteed by design.
22
PENTIUM PROCESSOR (610\75)
Table 11. Power Dissipation Requirements for Thermal Solution Design Parameter Active Power Dissipation Stop Grant and Auto Halt Powerdown Power Dissipation Stop Clock Power Dissipation .02 Typical (1) 3-4 8.0 1.2 .05 Max(2) Unit Watts Watts Watts Notes @ 75 MHz @ 75 MHz (3) (4) (5)
(R)
NOTES: 1. This is the typical power dissipation in a system. This value was the average value measured in a system using a typical device at Vcc = 3.3V running typical applications. This value is highly dependent upon the specific system configuration. 2. Systems must be designed to thermally dissipate the maximum active power dissipation. It is determined using a worstcase instruction mix with V cc = 3.3V. The use of nominal V cc in this measurement takes into account the thermal time constant of the package. 3. Stop Grant/Auto Halt Powerdown Power Dissipation is determined by asserting the STPCLK# pin or executing the HALT instruction. 4. Stop Clock Power Dissipation is determined by asserting the STPCLK# pin and then removing the external CLK input. 5. Complete characterization of the specification was still in process at the time of print. Please contact Intel for the latest information. The final specification may be less than 50 mW.
4.3. AC Specifications
The AC specifications of the Pentium processor (610\75) consist of setup times, hold times, and valid delays at 0 pF. WARNING Do not exceed the Pentium processor (610\75) internal maximum frequency of 75 MHz by either selecting the 1/2 bus fraction or providing a clock greater than 50 MHz. 4.3.1. POWER AND GROUND
performance. Inductance can be reduced by shortening circuit board traces between the Pentium processor (610\75) and decoupling capacitors as much as possible. These capacitors should be evenly distributed around each component on the 3.3V plane. Capacitor values should be chosen to ensure they eliminate both low and high frequency noise components. For the Pentium processor (610\75), the power consumption can transition from a low level of power to a much higher level (or high to low power) very rapidly. A typical example would be entering or exiting the Stop Grant state. Another example would be executing a HALT instruction, causing the Pentium processor (610\75) to enter the Auto HALT Powerdown state, or transitioning from HALT to the Normal state. All of these examples may cause abrupt changes in the power being consumed by the Pentium processor (610\75). Note that the Auto HALT Powerdown feature is always enabled even when other power management features are not implemented. Bulk storage capacitors with a low ESR (Effective Series Resistance) in the 10 to 100 range are f required to maintain a regulated supply voltage during the interval between the time the current load changes and the point that the regulated power supply output can react to the change in load. In order to reduce the ESR, it may be necessary to place several bulk storage capacitors in parallel. 23
For clean on-chip power distribution, the Pentium processor (610\75) has 79 Vcc (power) and 72 Vss (ground) inputs. Power and ground connections must be made to all external Vcc and Vss pins of the Pentium processor (610\75). On the circuit board all Vcc pins must be connected to a 3.3V Vcc plane. All V ss pins must be connected to a V ss plane. 4.3.2. DECOUPLING RECOMMENDATIONS
Liberal decoupling capacitance should be placed near the Pentium processor (610\75). The Pentium processor (610\75) driving its large address and data buses at high frequencies can cause transient power surges, particularly when driving large capacitive loads. Low inductance capacitors and interconnects are recommended for best high frequency electrical
PENTIUM PROCESSOR (610\75)
These capacitors should be placed near the Pentium processor (610\75) (on the 3.3V plane) to ensure that the supply voltage stays within specified limits during changes in the supply current during operation. 4.3.3. CONNECTION SPECIFICATIONS 4.3.4. AC TIMINGS FOR A 50-MHZ BUS
(R)
The AC specifications given in Table 12 consist of output delays, input setup requirements and input hold requirements for a 50-MHz external bus. All AC specifications (with the exception of those for the TAP signals and APIC signals) are relative to the rising edge of the CLK input. All timings are referenced to 1.5V for both "0" and "1" logic levels unless otherwise specified. Within the sampling window, a synchronous input must be stable for correct Pentium processor (610\75) operation.
All NC pins must remain unconnected. For reliable operation, always connect unused inputs to an appropriate signal level. Unused active low inputs should be connected to Vcc. Unused active high inputs should be connected to ground.
Table 12. Pentium (R) Processor (610\75) TCP AC Specifications for 50-MHz Bus Operation Vcc = 3.3V 5%, T CASE = 0 to 95 CL = 0 pF C C, Symbol Frequency t1a t1b t2 t3 t4 t5 t6a CLK Period CLK Period Stability CLK High Time CLK Low Time CLK Fall Time CLK Rise Time ADS#, PWT, PCD, BE0-7#, M/IO#, D/C#, CACHE#, SCYC, W/R# Valid Delay AP Valid Delay A3-A31, LOCK# Valid Delay 4.0 4.0 0.15 0.15 1.0 1.5 1.5 7.0 Parameter Min 25.0 20.0 Max 50.0 40.0 250 Unit MHz nS pS nS nS nS nS nS 3 3 3 3 4 3 (1), (19) @2V, (1) @0.8V, (1) (2.0V-0.8V), (1), (5) (0.8V-2.0V), (1), (5) Figure Notes Max Core Freq. = 75 MHz @ 2/3
t6b t6c
1.0 1.1
8.5 7.0
nS nS
4 4
24
PENTIUM PROCESSOR (610\75)
(R)
Table 12. Pentium (R) Processor (610\75) TCP AC Specifications for 50-MHz Bus Operation (Contd.) Vcc = 3.3V 5%, T CASE = 0 to 95 CL = 0 pF C C, Symbol t7 Parameter ADS#, AP, A3-A31, PWT, PCD, BE0-7#, M/IO#, D/C#, W/R#, CACHE#, SCYC, LOCK# Float Delay APCHK#, IERR#, FERR#, PCHK# Valid Delay BREQ, HLDA, SMIACT# Valid Delay HIT# Valid Delay HITM# Valid Delay PM0-1, BP0-3 Valid Delay PRDY Valid Delay D0-D63, DP0-7 Write Data Valid Delay D0-D63, DP0-3 Write Data Float Delay A5-A31 Setup Time A5-A31 Hold Time INV, AP Setup Time EADS# Setup Time EADS#, INV, AP Hold Time KEN# Setup Time NA#, WB/WT# Setup Time KEN#, WB/WT#, NA# Hold Time BRDY# Setup Time BRDY# Hold Time BOFF# Setup Time AHOLD Setup Time AHOLD, BOFF# Hold Time 6.5 1.0 5.0 6.0 1.0 5.0 4.5 1.0 5.0 1.0 5.5 6.0 1.0 1.0 1.0 1.0 1.1 1.0 1.0 1.3 Min Max 10.0 Unit nS Figure 5 (1) Notes
t8 t9a t10a t10b t11a t11b t12 t13 t14 t15 t16a t16b t17 t18a t18b t19 t20 t21 t22 t22a t23
8.3 8.0 8.0 6.0 10.0 8.0 8.5 10.0
nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS
4 4 4 4 4 4 4 5 6 6 6 6 6 6 6 6 6 6 6 6 6
(4) (4)
(1) (20)
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PENTIUM PROCESSOR (610\75)
(R)
Table 12. Pentium (R) Processor (610\75) TCP AC Specifications for 50-MHz Bus Operation (Contd.) Vcc = 3.3V 5%, T CASE = 0 to 95 CL = 0 pF C C, Symbol t24 t25 t25a t26 t27 t28 t29 t30 t31 t32 t33 t34 t35 t36 t37 t38 t39 t40 t41 Parameter BUSCHK#, EWBE#, HOLD, PEN# Setup Time BUSCHK#, EWBE#, PEN# Hold Time HOLD Hold Time A20M#, INTR, STPCLK# Setup Time A20M#, INTR, STPCLK# Hold Time INIT, FLUSH#, NMI, SMI#, IGNNE# Setup Time INIT, FLUSH#, NMI, SMI#, IGNNE# Hold Time INIT, FLUSH#, NMI, SMI#, IGNNE# Pulse Width, Async R/S# Setup Time R/S# Hold Time R/S# Pulse Width, Async. D0-D63, DP0-7 Read Data Setup Time D0-D63, DP0-7 Read Data Hold Time RESET Setup Time RESET Hold Time RESET Pulse Width, Vcc & CLK Stable RESET Active After Vcc & CLK Stable Reset Configuration Signals (INIT, FLUSH#) Setup Time Reset Configuration Signals (INIT, FLUSH#) Hold Time Min 5.0 1.0 1.5 5.0 1.0 5.0 1.0 2.0 5.0 1.0 2.0 3.8 2.0 5.0 1.0 15 1.0 5.0 1.0 Max Unit nS nS nS nS nS nS nS CLKs nS nS CLKs nS nS nS nS CLKs mS nS nS Figure 6 6 6 6 6 6 6 6 6 6 6 6 6 7 7 7 7 7 7 (11), (15) (12) (16) Power up (15), (16) (12) (11), (15) (12) (11), (15), (16) (12) (14), (16) (11), (15) (12) (14), (16) Notes
26
PENTIUM PROCESSOR (610\75)
(R)
Table 12. Pentium (R) Processor (610\75) TCP AC Specifications for 50-MHz Bus Operation (Contd.) Vcc = 3.3V 5%, T CASE = 0 to 95 CL = 0 pF C C, Symbol t42a Parameter Reset Configuration Signals (INIT, FLUSH#) Setup Time, Async. Reset Configuration Signals (INIT, FLUSH#, BRDY#, BUSCHK#) Hold Time, Async. Reset Configuration Signal (BRDY#, BUSCHK#) Setup Time, Async. Reset Configuration Signal BRDY# Hold Time, RESET driven synchronously BF Setup Time BF Hold Time APICEN Setup Time APICEN Hold Time TCK Frequency TCK Period TCK High Time TCK Low Time TCK Fall Time TCK Rise Time TRST# Pulse Width TDI, TMS Setup Time TDI, TMS Hold Time TDO Valid Delay TDO Float Delay All Non-Test Outputs Valid Delay 3.0 40.0 5.0 13.0 3.0 20.0 25.0 20.0 Min 2.0 Max Unit CLKs Figure 7 Notes To RESET falling edge (15) To RESET falling edge (211) To RESET falling edge (21) To RESET falling edge (1), (21) 7 7 7 7 (18) to RESET falling edge (18) to RESET falling edge To RESET falling edge To RESET falling edge
t42b
2.0
CLKs
7
t42c
3.0
CLKs
7
t42d
1.0
nS
t43a t43b t43c t43d t44 t45 t46 t47 t48 t49 t50 t51 t52 t53 t54 t55
1.0 2.0 2.0 2.0 -- 62.5 25.0 25.0 5.0 5.0 16.0
mS CLKs CLKs CLKs MHz nS nS nS nS nS nS nS nS nS nS nS
3 3 3 3 3 9 8 8 8 8 8 @2V, (1) @0.8V, (1) (2.0V- 0.8V), (1), (8), (9) (0.8V- 2.0V), (1), (8), (9) (1), Asynchronous (7) (7) (8) (1), (8) (3), (8), (10)
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PENTIUM PROCESSOR (610\75)
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Table 12. Pentium (R) Processor (610\75) TCP AC Specifications for 50-MHz Bus Operation (Contd.) Vcc = 3.3V 5%, T CASE = 0 to 95 CL = 0 pF C C, Symbol t56 t57 t58 Parameter All Non-Test Outputs Float Delay All Non-Test Inputs Setup Time All Non-Test Inputs Hold Time 5.0 13.0 Min Max 25.0 Unit nS nS nS Figure 8 8 8 Notes (1), (3), (8), (10) (3), (7), (10) (3), (7), (10)
APIC AC Specifications t60a t60b t60c t60d t60e t60f t60g t60h t60i t60j PICCLK Frequency PICCLK Period PICCLK High Time PICCLK Low Time PICCLK Rise Time PICCLK Fall Time PICD0-1 Setup Time PICD0-1 Hold Time PICD0-1 Valid Delay (LtoH) PICD0-1 Valid Delay (HtoL) 2.0 60.0 9.0 9.0 1.0 1.0 3.0 2.5 4.0 4.0 38.0 22.0 5.0 5.0 16.66 500.0 MHz nS nS nS nS nS nS nS nS nS 3 3 3 3 3 6 6 4 4 to PICCLK to PICCLK from PICCLK, (22) from PICCLK, (22)
NOTES: Notes 2, 6, and 14 are general and apply to all standard TTL signals used with the Pentium Processor family. 1. Not 100% tested. Guaranteed by design. 2. TTL input test waveforms are assumed to be 0 to 3V transitions with 1V/nS rise and fall times. 3. Non-test outputs and inputs are the normal output or input signals (besides TCK, TRST#, TDI, TDO, and TMS). These timings correspond to the response of these signals due to boundary scan operations. 4. APCHK#, FERR#, HLDA, IERR#, LOCK#, and PCHK# are glitch-free outputs. Glitch-free signals monotonically transition without false transitions (i.e., glitches). 5. 0.8V/ns CLK input rise/fall time 8V/ns. 6. 0.3V/ns input rise/fall time 5V/ns. 7. Referenced to TCK rising edge. 8. Referenced to TCK falling edge. 9. 1 ns can be added to the maximum TCK rise and fall times for every 10 MHz of frequency below 33 MHz. 10. During probe mode operation, do not use the boundary scan timings (t 55-58). 11. Setup time is required to guarantee recognition on a specific clock. 12. Hold time is required to guarantee recognition on a specific clock. 13. All TTL timings are referenced from 1.5V. 14. To guarantee proper asynchronous recognition, the signal must have been de-asserted (inactive) for a minimum of 2 clocks before being returned active and must meet the minimum pulse width. 15. This input may be driven asynchronously. 16. When driven asynchronously, RESET, NMI, FLUSH#, R/S#, INIT, and SMI# must be de-asserted (inactive) for a minimum of 2 clocks before being returned active. 17. The D/C#, M/IO#, W/R#, CACHE#, and A5-A31 signals are sampled only on the CLK that ADS# is active. 18. BF should be strapped to V cc or Vss.
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PENTIUM PROCESSOR (610\75)
These signals are measured on the rising edge of adjacent CLKs at 1.5V. To ensure a 1:1 relationship between the amplitude of the input jitter and the internal and external clocks, the jitter frequency spectrum should not have any power spectrum peaking between 500 KHz and 1/3 of the CLK operating frequency. The amount of jitter present must be accounted for as a component of CLK skew between devices. 20. Timing t14 is required for external snooping (e.g., address setup to the CLK in which EADS# is sampled active). 21. BUSCHK# is used as a reset configuration signal to select buffer size. 22. This assumes an external pullup resistor to V cc and a lumped capacitive load. The pullup resistor must be between 150 ohms and 1K ohms, the capacitance must be between 20 pF and 240 pF, and the RC product must be between 3 ns and 36 ns. ** Each valid delay is specified for a 0 pF load. The system designer should use I/O buffer modeling to account for signal flight time delays. 19.
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Figure 3. Clock Waveform
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PENTIUM PROCESSOR (610\75)
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Figure 4. Valid Delay Timings
Figure 5. Float Delay Timings
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PENTIUM PROCESSOR (610\75)
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Figure 6. Setup and Hold Timings
Figure 7. Reset and Configuration Timings
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Figure 8. Test Timings
Figure 9. Test Reset Timings
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PENTIUM PROCESSOR (610\75)
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4.4. I/O Buffer Models
This section describes the I/O buffer models of the Pentium processor (610\75) . The first order I/O buffer model is a simplified representation of the complex input and output buffers used in the Pentium processor (610\75). Figures 10 and 11 show the structure of the input buffer model and Figure 12 shows the output buffer model. Tables 13 and 14 show the parameters used to specify these models.
Although simplified, these buffer models will accurately model flight time and signal quality. For these parameters, there is very little added accuracy in a complete transistor model. The following two models represent the input buffer models. The first model, Figure 10, represents all of the input buffers of the Pentium processor (610\75) except for a special group of input buffers. The second model, Figure 11, represents these special buffers. These buffers are the inputs: AHOLD, EADS#, KEN#, WB/WT#, INV, NA#, EWBE#, BOFF#, CLK, and PICCLK.
Figure 10. Input Buffer Model, Except Special Group
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PENTIUM PROCESSOR (610\75)
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Figure 11. Input Buffer Model for Special Group
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PENTIUM PROCESSOR (610\75)
Table 13. Parameters Used in the Specification of the First Order Input Buffer Model Parameter Cin Lp Cp Rs D1, D2 Description Minimum and Maximum value of the capacitance of the input buffer model. Minimum and Maximum value of the package inductance. Minimum and Maximum value of the package capacitance. Diode Series Resistance Ideal Diodes
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Figure 12 shows the structure of the output buffer model. This model is used for all of the output buffers of the Pentium processor (610\75) .
Figure 12. First Order Output Buffer Model Table 14. Parameters Used in the Specification of the First Order Output Buffer Model Parameter dV/dt Ro Co Lp Cp Description Minimum and maximum value of the rate of change of the open circuit voltage source used in the output buffer model. Minimum and maximum value of the output impedance of the output buffer model. Minimum and Maximum value of the capacitance of the output buffer model. Minimum and Maximum value of the package inductance. Minimum and Maximum value of the package capacitance.
In addition to the input and output buffer parameters, input protection diode models are provided for added accuracy. These diodes have been optimized to provide ESD protection and provide some level of clamping. Although the diodes are not required for simulation, it may be more difficult to meet specifications without them.
Note, however, some signal quality specifications require that the diodes be removed from the input model. The series resistors (Rs) are a part of the diode model. Remove these when removing the diodes from the input model.
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PENTIUM PROCESSOR (610\75)
4.4.1. BUFFER MODEL PARAMETERS configurable output buffer EB2. Table 15 shows the drive level for BRDY# required at the falling edge of RESET to select the buffer strength. The buffer sizes selected should be the appropriate size required; otherwise AC timings might not be met, or too much overshoot and ringback may occur. There are no other selection choices; all of the configurable buffers get set to the same size at the same time.
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This section gives the parameters for each Pentium processor (610\75) input, output, and bidirectional signal, as well as the settings for the configurable buffers. Some pins on the Pentium processor (610\75) have selectable buffer sizes. These pins use the
Table 15. Buffer Selection Chart Environment Typical Stand Alone Component Loaded Component 1 0 BRDY# EB2 EB2A Buffer Selection
NOTES: For correct buffer selection, the BUSCHK# signal must be held inactive (high) at the falling edge of RESET. For the Pentium processor (610\75) SPGA version, BRDYC# is used to configure selectable buffer sizes.
Please refer to Table 16 for the groupings of the buffers. Table 16. Signal to Buffer Type Signals CLK A20M#, AHOLD, BF, BOFF#, BRDY#, BUSCHK#, EADS#, EWBE#, FLUSH#, HOLD, IGNNE#, INIT, INTR, INV, KEN#, NA#, NMI, PEN#, PICCLK, R/S#, RESET, SMI#, STPCLK#, TCK, TDI, TMS, TRST#, WB/WT# APCHK#, BE[7:5]#, BP[3:2], BREQ, FERR#, IERR#, PCD, PCHK#, PM0/BP0, PM1/BP1, PRDY, PWT, SMIACT#, TDO, U/O# A[31:21], AP, BE[4:0]#, CACHE#, D/C#, D[63:0], DP[8:0], HLDA, LOCK#, M/IO#, SCYC A[20:3], ADS#, HITM#, W/R# HIT# PID0, PICD1 The input, output and bidirectional buffer values are listed in Table 17. This table contains listings for all three types, do not get them confused during simulation. When a bidirectional pin is operating as Type I I Driver Buffer Type Receiver Buffer Type ER0 ER1
O
ED1
I/O I/O I/O I/O
EB1 EB2A EB3 EB4
EB1 EB2 EB3 EB4
an input, just use the Cin, Cp and Lp values; if it is operating as a driver, use all of the data parameters.
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PENTIUM PROCESSOR (610\75)
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Table 17. Input, Output and Bidirectional Buffer Model Parameters Buffer Type Transition min ER0 (input) ER1 (input) ED1 Rising Falling Rising Falling Rising 3/3.0 3/2.8 3/3.0 3/2.8 3/3.0 3/2.8 3/2.4 3/2.4 3/3.0 3/2.8 3/3.0 3/2.8 3.7/0.9 3.7/0.8 3.7/0.9 3.7/0.8 3.7/0.9 3.7/0.8 3.7/0.9 3.7/0.9 3.7/0.9 3.7/0.8 3.7/0.9 3.7/0.8 21.6 17.5 21.6 17.5 21.6 17.5 10.1 9.0 21.6 17.5 21.6 17.5 53.1 50.7 53.1 50.7 53.1 50.7 22.4 21.2 53.1 50.7 53.1 50.7 dV/dt (V/nsec) max Ro (Ohms) min max min 0.3 0.3 0.2 0.2 0.3 0.3 0.2 0.2 0.2 0.2 0.2 0.2 0.2 0.2 0.3 0.3 Cp (pF) max 0.4 0.4 0.5 0.5 0.6 0.6 0.5 0.5 0.5 0.5 0.5 0.5 0.4 0.4 0.4 0.4 min 3.9 3.9 3.1 3.1 3.7 3.7 2.9 2.9 3.1 3.1 3.1 3.1 3.2 3.2 4.0 4.0 Lp (nH) max 5.0 5.0 6.0 6.0 6.6 6.6 6.1 6.1 6.4 6.4 6.4 6.4 4.1 4.1 4.1 4.1 Co/Cin (pF) min 0.8 0.8 0.8 0.8 2.0 2.0 2.0 2.0 9.1 9.1 9.1 9.1 3.3 3.3 5.0 5.0 max 1.2 1.2 1.2 1.2 2.6 2.6 2.6 2.6 9.7 9.7 9.7 9.7 3.9 3.9 7.0 7.0
(output) Falling EB1 (bidir) EB2 (bidir) EB2A (bidir) EB3 (bidir) EB4 (bidir) Rising Falling Rising Falling Rising Falling Rising Falling Rising Falling
Table 18. Input Buffer Model Parameters: D (Diodes) Symbol IS N RS TT VJ CJ0 M Parameter Saturation Current Emission Coefficient Series Resistance Transit Time PN Potential Zero Bias PN Capacitance PN Grading Coefficient 1.4e-14A 1.19 6.5 ohms 3 ns 0.983V 0.281 pF 0.385 D1 D2 2.78e-16A 1.00 6.5 ohms 6 ns 0.967V 0.365 pF 0.376
4.4.2.
SIGNAL QUALITY SPECIFICATIONS
Signals driven by the system into the Pentium processor (610\75) must meet signal quality specifications to guarantee that the components
read data properly and to ensure that incoming signals do not affect the reliability of the component. There are two signal quality parameters: Ringback and Settling Time. 37
PENTIUM PROCESSOR (610\75)
4.4.2.1. Ringback Excessive ringback can contribute to long-term reliability degradation of the Pentium processor (610\75), and can cause false signal detection. Ringback is simulated at the input pin of a component using the input buffer model. Ringback can be simulated with or without the diodes that are in the input buffer model. Ringback is the absolute value of the voltage at the receiving pin below Vcc Vss) relative to Vcc (or Vss) level after has reached its maximum voltage level. diodes are assumed present. maximum (or above the signal The input meeting the overshoot/undershoot specification, the signal is guaranteed not to ringback excessively. If simulated with the diodes present in the input model, follow the maximum ringback specification. Overshoot (Undershoot) is the absolute value of the maximum voltage above Vcc (below Vss). The guideline assumes the absence of diodes on the input. * Maximum Overshoot/Undershoot on 5V 82497 Cache Controller, and 82492 Cache SRAM Inputs (CLK and PICCLK only) = 1.6V above VCC5 (without diodes) * Maximum Overshoot/Undershoot on 3.3V Pentium processor (610\75) Inputs (not CLK and PICCLK) = 1.4V above V CC3 (without diodes)
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Maximum Ringback on Inputs = 0.8V (with diodes) If simulated without the input diodes, follow the Maximum Overshoot/Undershoot specification. By
Figure 13. Overshoot/Undershoot and Ringback Guidelines 4.4.2.2. Settling Time The settling time is defined as the time a signal requires at the receiver to settle within 10 percent of Vcc or Vss. Settling time is the maximum time allowed for a signal to reach within 10 percent of its final value. Most available simulation tools are unable to simulate settling time so that it accurately reflects silicon measurements. On a physical board, 38 second-order effects and other effects serve to dampen the signal at the receiver. Because of all these concerns, settling time is a recommendation or a tool for layout tuning and not a specification. Settling time is simulated at the slow corner, to make sure that there is no impact on the flight times of the signals if the waveform has not settled. Settling time
PENTIUM PROCESSOR (610\75)
may be simulated with the diodes included or excluded from the input buffer model. If diodes are included, settling time recommendation will be easier to meet. Although simulated settling time has not shown good correlation with physical, measured settling time, settling time simulations can still be used as a tool to tune layouts. Use the following procedure to verify board simulation and tuning with concerns for settling time. 1. Simulate settling time at the slow corner for a particular signal. 2. If settling time violations occur, simulate signal trace with D.C. diodes in place at the receiver pin. The D.C. diode behaves almost identically to the actual (non-linear) diode on the part as long as excessive overshoot does not occur. 3. If settling time violations still occur, simulate flight times for 5 consecutive cycles for that particular signal. 4. If flight time values are consistent over the 5 simulations, settling time should not be a concern. If however, flight times are not consistent over the 5 simulations, tuning of the layout is required. 5. Note that, for signals that are allocated 2 cycles for flight time, the recommended settling time is doubled. A typical design method would include a settling time that ensures a signal is within 10% of VCC or VSS for at least 2.5 ns prior to the end of the CLK period.
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Figure 14. Settling Time
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PENTIUM PROCESSOR (610\75)
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5.0. Pentium Processor (610\75) TCP MECHANICAL SPECIFICATIONS
Today's portable computers face the challenge of meeting desktop performance in an environment that is constrained by thermal, mechanical, and electrical design considerations. These considerations have driven the development and implementation of Intel' Tape Carrier Package s (TCP). The Intel TCP package has been designed to offer a high pin count, low profile, reduced footprint package with uncompromised thermal and electrical performance. Intel continues to provide packaging solutions that meet our rigorous criteria for quality and performance, and this new entry into the Intel package portfolio is no exception. Key features of the TCP package include: surface mount technology design, lead pitch of 0.25 mm, polyimide body size of 24 mm and polyimide up for
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pick&place handling. TCP components are shipped with the leads flat in slide carriers, and are designed to be excised and lead formed at the customer manufacturing site. Recommendations for the manufacture of this package are included in the Pentium(R) Processor (610\75) Tape Carrier Package User' Guide. s Figure 15 shows a cross-sectional view of the TCP package as mounted on the Printed Circuit Board. Figures 16 and 17 show the TCP as shipped in its slide carrier, and key dimensions of the carrier and package. Figure 18 shows a blow up detail of the package in cross-section. Figure 19 shows an enlarged view of the outer lead bond area of the package. Tables 19 and 20 provide Pentium processor (610\75) TCP package dimensions.
5.1. TCP Package Mechanical Diagrams
Polyimide Support Ring Polyimide Keeper Bar
Encapsulant Gold Bump
TAB Lead (OFC Copper)
Die PCB 1/2 X-Section Thermally & Electrically Conductive Adhesive (Silver Filled Thermoplastic) Thermal vias Ground plane Note: Sketches Not to Scale
PCB Full X-Section
Figure 15. Cross-Sectional View of the Mounted TCP Package
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PENTIUM PROCESSOR (610\75)
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Figure 16. One TCP Site in Carrier (Bottom View of Die)
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PENTIUM PROCESSOR (610\75)
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Figure 17. One TCP Site in Carrier (Top View of Die)
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PENTIUM PROCESSOR (610\75)
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Figure 18. One TCP Site (Cross-Sectional Detail)
Figure 19. Outer Lead Bond (OLB) Window Detail
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PENTIUM PROCESSOR (610\75)
Table 19. TCP Key Dimensions Symbol Symbol N W L e1 b D1,E1 A2 DL DW LT EL EW Leadcount Tape Width Site Length Outer Lead Pitch Outer Lead Width Package Body Size Package Height Die Length Die Width Lead Thickness Encap Length Encap Width Description Description 320 leads 48.18 0.12 (43.94) reference only 0.25 nominal 0.10 0.01 24.0 0.1 75 MHz/90 MHz--0.615 0.030 120 MHz--0.605 0.030 75 MHz/90 MHz--12.769 0.015 120 MHz--9.929 0.015 75 MHz/90 MHz--11.755 0.015 120 MHz--9.152 0.015 75 MHz/90 MHz--0.035 mm 120 MHz--0.025 mm 75 MHz/90 MHz--(13.40 mm) reference only 120 MHz--(10.56 mm) reference only 75 MHz/90 MHz--(12.39 mm) reference only 120 MHz--(9.78 mm) reference only Dimension Dimension
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NOTES: Dimensions are in millimeters unless otherwise noted. Dimensions in parentheses are for reference only.
Table 20. Mounted TCP Package Dimensions Description Package Height Terminal Dimension Package Weight 0.75 max. 29.5 nom. 0.5 g max. Dimension
NOTE: Dimensions are in millimeters unless otherwise noted. Package terminal dimension (lead tip-to-lead tip) assumes the use of a keeper bar.
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PENTIUM PROCESSOR (610\75)
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6.0. Pentium Processor (610\75) TCP THERMAL SPECIFICATIONS
The Pentium processor (610\75) is specified for proper operation when the case temperature, TCASE, (TC) is within the specified range of 0 to C 95 C.
where,
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TJ = TC + P xJC TA = TJ - P xJA TA = TC - ( P xCA) TC = TA + P x[JA - JC] CA = JA - JC
6.1. Measuring Thermal Values
To verify that the proper TC (case temperature) is maintained for the Pentium processor (610\75), it should be measured at the center of the package top surface (encapsulant). To minimize any measurement errors, the following techniques are recommended: * Use 36 gauge or finer diameter K, T, or J type thermocouples. Intel's laboratory testing was done using a thermocouple made by Omega (part number: 5TC-TTK-36-36). * Attach the thermocouple bead or junction to the center of the package top surface using highly thermally conductive cements. Intel's laboratory testing was done by using Omega Bond (part number: OB-100). * The thermocouple should be attached at a 90 angle as shown in Figure 20.
TA and TC are ambient and case temperatures ( C) CA = Case-to-Ambient thermal resistance ( C/W) JA = Junction-to-Ambient thermal resistance ( C/W) JC = Junction-to-Case thermal resistance ( C/W) P = maximum power consumption (Watts)
P (maximum power consumption) is specified in section 4.2.
6.3. TCP Thermal Characteristics
The primary heat transfer path from the die of the Tape Carrier Package (TCP) is through the back side of the die and into the PC board. There are two thermal paths traveling from the PC board to the ambient air. One is the spread of heat within the board and the dissipation of heat by the board to the ambient air. The other is the transfer of heat through the board and to the opposite side where thermal enhancements (e.g., heat sinks, pipes) are attached. To prevent the possibility of damaging the TCP component, the thermal enhancements should be attached to the opposite side of the TCP site -- not directly mounted to the package surface.
6.4. PC Board Enhancements
Copper planes, thermal pads, and vias are design options that can be used to improve heat transfer from the PC board to the ambient air. Tables 21 and 22 present thermal resistance data for copper plane thickness and via effects. It should be noted that although thicker copper planes will reduce the ca of a system without any thermal enhancements, they have less effect on the ca of a system with thermal enhancements. However, placing vias under the die will reduce the ca of a system with and without thermal enhancements.
Figure 20. Technique for Measuring Case Temperature (T C)
6.2. Thermal Equations
For the Pentium processor (610\75), an ambient temperature (TA) is not specified directly. The only requirement is that the case temperature (TC) is met. The ambient temperature can be calculated from the following equations:
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PENTIUM PROCESSOR (610\75)
Table 21. Thermal Resistance vs. Copper Plane Thickness with and without Enhancements Copper Plane Thickness* 1 oz. Cu 3 oz. Cu CA ( C/W) No Enhancements 18 14 8 8 CA ( C/W) With Heat Pipe NOTE Thermal resistance values should be used as guidelines only, and are highly system dependent. Final system verification should always refer to the case temperature specification. Table 23. Pentium (R) Processor (610\75) TCP Package Thermal Resistance without Enhancements JC ( C/W) Thermal Resistance without .8 Enhancements CA ( C/W) 13.9
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NOTES: *225 vias underneath the die (1 oz = 1.3 ml)
Table 22. Thermal Resistance vs. Thermal Vias underneath the Die No. of Vias Under the Die* 0 144 15 13 CA ( C/W) No Enhancements
Table 24. Pentium (R) Processor (610\75) TCP Package Thermal Resistance with Enhancements (without Airflow) CA Thermal Enhancements Heat sink Al Plate ( C/W) 11.7 8.7 7.8 Notes 1.2"x1.2"x.35" 4"x4"x.030" .3x1"x4"
NOTE: *3 oz. copper planes in test boards
6.4.1.
STANDARD TEST BOARD CONFIGURATION
Al Plate with Heat Pipe
All Tape Carrier Package (TCP) thermal measurements provided in the following tables were taken with the component soldered to a 2" x 2" test board outline. This six-layer board contains 225 vias (underneath the die) in the die attach pad which are connected to two 3 oz. copper planes located at layers two and five. For the Pentium processor (610\75) TCP, the vias in the die attach pad should be connected without thermal reliefs to the ground plane(s). The die is attached to the die attach pad using a thermally and electrically conductive adhesive. This test board was designed to optimize the heat spreading into the board and the heat transfer through to the opposite side of the board.
Table 25. Pentium (R) Processor (610\75) TCP Package Thermal Resistance with Enhancements (with Airflow) Thermal Enhancements Heat sink with Fan @ 1.7 CFM Heat sink with Airflow @ 400 LFM Heat sink with Airflow @ 600 LFM
HS = heat sink LFM = Linear Feet/Minute CFM = Cubic Feet/Minute
CA ( C/W) 5.0 Notes 1.2"x1.2"x.35" HS 1"x1"x.4" Fan 5.1 4.3 1.2"x1.2"x.35" HS 1.2"x1.2"x.35" HS
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